The reset function is a fundamental operation for every microprocessor system. Because each system switch-on begins with an auto-reset/power-good signal. Obviously each time is needed to any microprocessor system the restart operation, a correct reset function is required. — Well, but someone may say:yet still another reset circuit, why this circuit?
Anyone who has “googled” for finding a reset circuit capable to be a power-good wait also, often gets from Internet circuits made with big capacitors, connected with rough (short-circuit) to the ground. — Those wrong interfacing techniques aren’t the only one capable of solving this problem, so I take some time for think to a simple solution for give my answer to the question. — The first project obligation is to have about 900mS with capacitors not bigger than 22uF, the second obligation is remove shock current of discharge from capacitors, while the reset button is pressed. — And for finish the capability of re-trigger the signal or enlarge the time of action with toggling to the button many times in the same manner of an air-pump. —
Simply in short words: if capacitors life is good, your system-processor board could live better.
Reset schematic circuit, theory of operation
Simply looking the schema of the circuit, from left to right it’s easy to note the softly metamorphosis from analog or discrete components to the digital counterparts on the right area. It seems like an Escher paint, in which some fish are becalming bird. Well this circuit does not was made to be fitted to the wall, so let us begin to describe how does it works.
Discrete (analogical part) analysis
On the left-part we can see a parallel connection between the resistor R1 and the diode D1 placed on the action button. It’s easy to study the behavior of this part so we can go on and analyze the exact time when the button is pressed, Now we have a capacitor C1 connected in parallel with a voltage source of 0,65V (Reverse voltage of the diode D1) and not with a direct zero volt connection, the resistor R1 gives a minor contribute to upper this threshold. So we have removed the shock current from first capacitor of this circuit.
Proceeding along the connection signal we find a series connection between R2 and D2 this connection assures a branch voltage of V(R2) + 0.65V to add on the first branch of + 0.65V to ground. Obviously the resistor R2 is used as a current flow limit, in each two the cases in discharge and in recharge time. It’s clear the concept that we have about 1.3Volts on capacitor C2, so there is no shock current at all on this capacitor, and recharge time depends to the current flowing across only one resistor the R3 (Reset time regulator).
Digital area analysis
Before to begin the analysis of the digital part, someone may think that _SET and _RES should be simultaneously down for about 20 nS, the time needed to the schmitt trigger not IC1a to be raised when each two diodes D3 and D4 are directly connected from 1,3 Volts – 0,65V, so giving about 0,65V on IC1a and on _RES pin of Filp Flop IC2a.
Well a preceding version was a little tricky and had some more resistors on D3 and D4 to avoid to this case to happen, those resistors was removed. This happened during tests made on the last preceding revision, because the time of 20 nS was no-influent respect to period of 900mS. And for finish the components tested never produces the glitch out for a so short time, seems that the flip-flop has inside a short time-constant that harmonize this phenomenon that never happens, or better has no observed anomalies. So follows the optimizations made for this version is proved as steady and stable.
Here we are at the end of the circuit, here we can see that this was done for Z80 and for Intel 8086 reset/power-good type because form IC1b could be taken the Intel active high reset, and from IC1c could be taken the signal for Aleph-Z80 active low.
NOTE: do not change the 74HC14 with 74HC04, the optimization was made strictly for this component. (The circuit was not proved with TTL STD logic, but may work fine).
FOR MORE INFO: Z80 & aleph work group
Follows the source files in fidocadJ this can be modified and used without restrictions, format. — Use is at your own risk the author is not responsible of any damages. —